sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 319

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in
9.3.2.5
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
Freescale Semiconductor
Module Base + 0x0004
Reset:
W
R
1. This setting is not valid. Please refer to
MSCAN Receiver Flag Register (CANRFLG)
WUPIF
TSEG13
Bit Time
1. This setting is not valid. Please refer to
0
7
0
0
0
0
1
1
:
TSEG22
0
0
1
1
:
Figure 9-8. MSCAN Receiver Flag Register (CANRFLG)
= Unimplemented
CSCIF
=
6
0
TSEG12
----------------------------------------------------- -
MC9S12HY/HA-Family Reference Manual Rev. 1.04
Prescaler value
0
0
0
0
1
1
:
f CANCLK
TSEG21
Table 9-10. Time Segment 1 Values
Table 9-9. Time Segment 2 Values
RSTAT1
0
0
1
1
:
0
5
TSEG11
0
0
1
1
1
1
:
Table 9-9
Table 9-37
TSEG20
RSTAT0
Table 9-37
4
0
0
1
0
1
:
1
TSEG10
+
and
Freescale’s Scalable Controller Area Network (S12MSCANV3)
for valid settings.
TimeSegment1
0
1
0
1
0
1
:
Table
for valid settings.
TSTAT1
0
3
9-10).
1 Tq clock cycle
Time Segment 2
2 Tq clock cycles
7 Tq clock cycles
8 Tq clock cycles
1 Tq clock cycle
15 Tq clock cycles
16 Tq clock cycles
2 Tq clock cycles
3 Tq clock cycles
Time segment 1
4 Tq clock cycles
TSTAT0
:
2
0
+
TimeSegment2
:
(1)
Access: User read/write
(1)
OVRIF
1
1
0
1
Eqn. 9-1
RXF
0
0
319
(1)