sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 365

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

10.3.1.1
Read and write anytime
This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not
the address sent on the bus during the address transfer.
10.3.1.2
Read and write anytime
Freescale Semiconductor
Reserved
ADR[7:1]
IBC[7:0]
Reset
Reset
Field
Field
7:1
7:0
0
W
W
R
R
Module Base +0x0000
Module Base + 0x0001
ADR7
IBC7
Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default
mode of IIC bus is slave mode for an address match on the bus.
Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.
I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and
IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown
in
IIC Address Register (IBAD)
IIC Frequency Divider Register (IBFD)
0
0
7
7
Table
10-4.
= Unimplemented or Reserved
ADR6
IBC6
Figure 10-4. IIC Bus Frequency Divider Register (IBFD)
= Unimplemented or Reserved
0
0
6
6
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Figure 10-3. IIC Bus Address Register (IBAD)
Table 10-2. IBAD Field Descriptions
Table 10-3. IBFD Field Descriptions
ADR5
IBC5
0
0
5
5
ADR4
IBC4
0
0
4
4
Description
Description
ADR3
IBC3
0
0
3
3
Inter-Integrated Circuit (IICV3) Block Description
ADR2
IBC2
0
0
2
2
ADR1
IBC1
0
0
1
1
IBC0
0
0
0
0
0
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