sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 258

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
7.3.2.19
The CPMUHTTR register configures the trimming of the S12CPMU temperature sense.
Read: Anytime
Write: Anytime
258
0x02F7
After de-assert of System Reset a trim value is automatically loaded from the Flash memory. See Device specification for
HTTR[3:0]
Reset
HTOE
Field
details.
3–0
7
W
R
HTOE
High Temperature Offset Enable Bit — If set the temperature sense offset is enabled.
0 The temperature sense offset is disabled. HTTR[3:0] bits don’t care.
1 The temperature sense offset is enabled. HTTR[3:0] select the temperature offset.
High Temperature Trimming Register (CPMUHTTR)
High Temperature Trimming Bits — See
0
7
= Unimplemented or Reserved
HTTR[3]
HTTR[2]
HTTR[1]
HTTR[0]
0
0
6
Bit
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Increases V
Increases V
Increases V
Increases V
0
0
5
HT
HT
HT
HT
twice of HTTR[2]
twice of HTTR[1]
twice of HTTR[0]
(to compensate Temperature Offset)
Table 1-27
0
0
4
Trimming Effect
Description
for trimming effects.
HTTR3
F
3
HTTR2
F
2
HTTR1
Freescale Semiconductor
F
1
HTTR0
F
0