sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 497

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sc9s12hy64j0vllr

Manufacturer Part Number
sc9s12hy64j0vllr
Description
S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
Manufacturer
Freescale Semiconductor, Inc
Datasheet
14.3.2.8
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0008
Module Base + 0x0009
Reset
Reset
Field
OMx
OLx
7:0
7:0
W
W
R
R
OM7
OM3
Output Mode — These eight pairs of control bits are encoded to specify the output action to be taken as a result
of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: To enable output action by OMx bits on timer port, the corresponding bit in OC7M should be cleared. For
Output Level — These eight pairs of control bits are encoded to specify the output action to be taken as a result
of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: To enable output action by OLx bits on timer port, the corresponding bit in OC7M should be cleared. For
Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)
0
0
7
7
an output line to be driven by an OCx the OCPDx must be cleared.
an output line to be driven by an OCx the OCPDx must be cleared.
OMx
OL7
OL3
0
0
6
6
0
0
1
1
Figure 14-14. Timer Control Register 1 (TCTL1)
Figure 14-15. Timer Control Register 2 (TCTL2)
MC9S12HY/HA-Family Reference Manual Rev. 1.04
Table 14-8. TCTL1/TCTL2 Field Descriptions
Table 14-9. Compare Result Output Action
OM6
OM2
OLx
0
1
0
1
0
0
5
5
OL6
OL2
0
0
4
4
action on the timer output signal
Clear OCx output line to zero
Description
Set OCx output line to one
Toggle OCx output line
No output compare
OM5
OM1
Action
0
0
3
3
Timer Module (TIM16B8CV2) Block Description
OL5
OL1
0
0
2
2
OM4
OM0
0
0
1
1
OL4
OL0
0
0
0
0
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