sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 73

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sc9s12hy64j0vllr

Manufacturer Part Number
sc9s12hy64j0vllr
Description
S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1
2.3.6
Freescale Semiconductor
Address 0x0003 (PRR)
Read: Anytime
Write: Anytime
DDRA
DDRA
DDRA
DDRA
Field
7-4,2
Reset
3
1
0
W
R
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disable
1 Associated pin is configured as output
0 Associated pin is configured as input
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else if API_EXTCLK is enabled, it will be forced as output
1 Associated pin is configured as output
0 Associated pin is configured as input
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else if XIRQ is enabled, it will be forced as input
1 Associated pin is configured as output
0 Associated pin is configured as input
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else if /IRQ is enabled, it will be forced as input
1 Associated pin is configured as output
0 Associated pin is configured as input
DDRB7
Port B Data Direction Register (DDRB)
0
7
DDRB6
0
6
Figure 2-4. Port B Data Direction Register (DDRB)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 2-6. DDRA Register Field Descriptions
DDRB5
0
5
DDRB4
0
4
Description
DDRB3
3
0
DDRB2
Port Integration Module (S12HYPIMV1)
0
2
DDRB1
Access: User read/write
0
1
DDRB0
0
0
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