ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 102

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
SPIF
6
WCOL
5
4
MODF
[3:0]
SPI Status Register
The SPI Status Read Only register, indicated in
data transmitted using the serial peripheral interface. Reading the SPIx_SR regis-
ter clears bits 7, 6, and 4 to a logical 0.
SPI Transmit Shift Register
The SPI Transmit Shift register (SPIx_TSR) is used by the SPI master to transmit
data onto the SPI serial bus to the slave device. A write to the SPIx_TSR register
places data directly into the shift register for transmission. A write to this register
within an SPI device configured as a master initiates transmission of a byte of the
data loaded into the register. After completing this transmission, the SPIF status
bit (SPIx_SR[7]) is set to 1 in both the master and slave devices.
The SPI Transmit Shift Write Only registers share the same address space as the
SPI Receive Buffer Read Only registers.
Value Description
0
1
0
1
0
0
1
0000b Reserved—must be 0.
(SPI0_SR = B7h, SPI1_SR = BBh)
The SPI data transfer is not finished.
The SPI data transfer is finished. If enabled, an interrupt is
generated. This bit flag is cleared to 0 by a read of the
SPIx_SR register.
An SPI write collision is not detected.
An SPI write collision is detected. This bit flag is cleared to 0
by a read of the SPIx_SR registers.
Reserved—must be 0.
A mode fault (multimaster conflict) is not detected.
A mode fault (multimaster conflict) is detected. This bit flag is
cleared to 0 by a read of the SPIx_SR register.
R
7
0
Table 40. SPI Status Register
R
6
0
PRELIMINARY
R
5
0
R
4
0
R
3
0
Table
eZ80190 Product Specification
40, returns the status of
R
2
1
Serial Peripheral Interface
R
1
0
R
0
0
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