ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 92

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
ERR
6
TEMT
5
THRE
4
BI
UART Line Status Registers
These registers are used to show the status of UART interrupts and registers.
Value
0
1
0
1
0
1
0
1
(UART0_LSR = C5h, UART1_LSR = D5h)
Table 35. UART Line Status Registers
Description
This bit is always 0 when operating with the FIFO disabled.
With the FIFO enabled, this bit is reset when the UARTx_LSR
register is read and there are no more bytes with an error
status in the FIFO.
An error is detected in the FIFO. There is at least 1 parity,
framing, or Break Indication (BI) error in the FIFO.
The Transmit Holding Register FIFO is not empty, the
Transmit Shift Register is not empty, or the transmitter is not
idle.
The Transmit Holding Register FIFO and the Transmit Shift
Register are empty; the transmitter is idle. This bit cannot be
set to 1 during the Break Indication (BI). This bit is set to 1
only after the BREAK command is removed.
The Transmit Holding Register FIFO is not empty.
The Transmit Holding Register FIFO bit cannot be set to 1
during the Break Indication (BI). This bit is set to 1 only after
the BREAK command is removed.
The receiver does not detect a Break Indication. This bit is
reset to 0 when the UARTx_LSR register is read.
The receiver detects a Break Indication on the receive input
line. This bit is set to 1 if the duration of the Break Indication
on the receive data is longer than one character transmission
time, the time depends on the programming of the
UARTx_LSR register. In the case of a FIFO, only one null
character is loaded into the receive FIFO with the framing
error. The framing error is revealed to the eZ80
this particular string of data is read from the receive FIFO.
R
7
0
R
6
1
PRELIMINARY
R
5
1
R
4
0
Universal Asynchronous Receiver/Transmitter
R
3
0
eZ80190 Product Specification
R
2
0
®
whenever
R
1
0
R
0
0
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