ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 104

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

I
PS006613-0306
2
C Serial I/O Interface
I
2
C General Characteristics
The I
four modes:
•
•
•
•
The I
Both SDA and SCL are bidirectional lines, connected to a positive supply voltage
via an external pull-up resistor. When the bus is free, both lines are High. The out-
put stages of devices connected to the bus must be configured as open-drain out-
puts. Data on the I
STANDARD mode, or up to 400 kbps in FAST mode. One clock pulse is gener-
ated for each data bit transferred.
Clocking Overview
If another device on the I
MASTER mode, the I
period of the clock is determined by the device that generates the shortest High
clock period. The Low period of the clock is determined by the device that gener-
ates the longest Low clock period.
A slave may stretch the Low period of the clock to slow down the bus master. The
Low period can also be stretched for handshaking purposes. For both circum-
stances, this Low period can be stretched after each bit transfer or each byte
transfer. The I
the I2Cx_CTL register is cleared.
Bus Arbitration Overview
In MASTER mode, the I
I
nal Low, arbitration is lost. If arbitration is lost during the transmission of a data
byte or a NACK bit, the I
transmission of an address, the I
nize its own slave address or the general call address.
2
C bus as a logic 1. If another device on the bus overrules and pulls the SDA sig-
MASTER TRANSMIT
MASTER RECEIVE
SLAVE TRANSMIT
SLAVE RECEIVE
2
2
C serial I/O bus is a two-wire communication interface that can operate in
C interface consists of the Serial Clock (SCL) and the Serial Data (SDA).
2
C stretches the clock after each byte transfer until the IFLG bit in
2
C bus can be transferred at a rate of up to 100 kbps in
2
C synchronizes its clock to the I
2
2
2
C checks that each transmitted logic 1 appears on the
C returns to the IDLE state. If arbitration is lost during the
C bus drives the clock line when the I
PRELIMINARY
2
C switches to SLAVE mode so that it can recog-
2
C bus clock. The High
I
2
2
C is operating in
C Serial I/O Interface
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