ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 96

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

Serial Peripheral Interface
PS006613-0306
Baud Rate
Generator
SPI Signals
Bit 7
The Serial Peripheral Interface (SPI) is a synchronous interface allowing several
SPI-type devices to be interconnected. The SPI is a full-duplex, synchronous,
character-oriented communication channel that employs a four-wire interface. The
SPI block consists of a transmitter, receiver, clock generator, and control unit. Dur-
ing an SPI transfer, data is sent and received simultaneously by both the master
and the slave SPI devices.
In a serial peripheral interface, separate signals are required for data and clock.
The eZ80190 device contains two SPI devices—one within each Universal ZiLOG
Interface (UZI) block. The SPI devices may be configured as either master or
slave. The connection of two SPI devices (one master and one slave) and the
direction of data transfer is demonstrated in
The four basic SPI signals (MISO, MOSI, SS, and SCK) are discussed in the fol-
lowing paragraphs. Each signal is described in both MASTER and SLAVE modes.
Master In Slave Out
The Master In Slave Out (MISO) pin is configured as an input in a master device
and as an output in a slave device. It is one of the two lines that transfer serial
data, with the most significant bit sent first. The MISO pin of a slave device is
8-bit Shift Register
Master
Figure 13. SPI Master
Bit 0
PRELIMINARY
MISO
MOSI
SCK
—Slave Connection
MISO
MOSI
SCK
Figure
Bit 7
eZ80190 Product Specification
13.
8-bit Shift Register
Slave
Serial Peripheral Interface
Bit 0
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