ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 59

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

eZ80190 Product Specification
45
open-source mode, an external pull-down resistor must connect the pin to the
supply ground. Writing a 1 to the Port x Data register outputs a High at the pin.
Writing a 0 to the Port x Data register results in a high-impedance output.
GPIO Mode 5. Reserved. This pin produces high-impedance output.
GPIO Mode 6. The bit enables a dual-edge-triggered interrupt mode. Both a rising
and a falling edge on the pin cause an interrupt request to be sent to the CPU.
Writing a 1 to the Port x Data register bit position resets the corresponding inter-
rupt request. Writing a 0 produces no effect. The programmer must set the Port x
Data register before entering the dual-edge-triggered interrupt mode.
GPIO Mode 7. For Ports C and D, the port pin is configured to pass control over to
the alternate functions assigned to the pin. For example, the alternate mode func-
tion for PC7 is RI1. When GPIO Mode 7 is enabled, the pin output data and pin
tristate control come from the alternate function's data output and tristate control,
respectively. The value in the Port x Data register produces no effect on operation.
For Ports A and B, which do not feature alternate I/O functions, selecting GPIO
Mode 7 results in a configuration of the pins for input from the pin and high-imped-
ance output as in GPIO Mode 2.
GPIO Mode 8. The port pin is configured for level-sensitive interrupt modes. An
interrupt request is generated when the level at the pin is the same as the level
stored in the Port x Data register. The port pin value is sampled by the system
clock. The input pin must be held at the selected interrupt level for a minimum of 2
clock periods to initiate an interrupt. The interrupt request remains active as long
as this condition is maintained at the external source.
GPIO Mode 9. The port pin is configured for single-edge-triggered interrupt mode.
The value in the Port x Data register determines if a positive or negative edge
causes an interrupt request. A 0 in the Port x Data register bit sets the selected
pin to generate an interrupt request for falling edges. A 1 in the Port x Data regis-
ter bit sets the selected pin to generate an interrupt request for rising edges. The
interrupt request remains active until a 1 is written to the Port x Data register bit’s
corresponding interrupt request. Writing a 0 produces no effect on operation. The
programmer must set the Port x Data register before entering the single-edge-trig-
gered interrupt mode.
A simplified block diagram of a GPIO port pin is illustrated in
Figure
7.
PS006613-0306
PRELIMINARY
General-Purpose Input/Output