ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 55

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
7
WDT_EN
6
NMI_OUT
5
RST_FLAG
[4:2]
[1:0]
WDT_PERIOD
Value Description
0
1
0
1
0
1
000
00
01
10
11
Table 10. Watch-Dog Timer Control Register
R/W
WDT is disabled.
WDT is enabled. When enabled, the WDT cannot be disabled
without a full-chip reset.
WDT time-out resets the CPU.
WDT time-out generates a nonmaskable interrupt (NMI) to the
CPU.
RESET caused by external full-chip reset or ZDI reset.
RESET caused by WDT time-out. This flag is set by the WDT
time-out, even if the NMI_OUT flag is set to 1. The CPU can
poll this bit to determine the source of the RESET or NMI.
Reserved.
WDT time-out period is 134,217,728 (2
WDT time-out period is 33,554,432 (2
WDT time-out period is 4,194,304 (2
WDT time-out period is 262,144 (2
7
0
R/W
(WDT_CTL = 93h)
6
0
PRELIMINARY
0/1
R
5
R
4
0
R
3
0
18
eZ80190 Product Specification
22
) clock cycles.
25
) clock cycles.
27
) clock cycles.
) clock cycles.
R
2
0
R/W
1
0
Watch-Dog Timer
R/W
0
0
41