ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 35
ez80190
Manufacturer Part Number
ez80190
Description
Ez80190 Microprocessor
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80190.pdf
(222 pages)
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PS006613-0306
Pin # Symbol
95
96
97
98
99
100
PA6
PA7
V
GND
BUSREQ Bus Request
PHI
DD
Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued)
Function
GPIO Port A
GPIO Port A
Power Supply
Ground
System Clock Output
Signal Direction
Input/Output
Input/Output
Input, Active Low
PRELIMINARY
Description
The PA6 pin can be used for general-purpose I/O.
It can be individually programmed as an input or
an output and can also be used individually as an
interrupt input. Each Port A pin, when
programmed as an output, can be selected to be
an open-drain or open-source output.
The PA7 pin can be used for general-purpose I/O.
It can be individually programmed as an input or
an output and can also be used individually as an
interrupt input. Each Port A pin, when
programmed as an output, can be selected to be
an open-drain or open-source output.
Power Supply
Ground
External devices can force the eZ80190 device to
release the bus for their use by driving this line
Low. To the CPU, the bus request signal can also
originate from internal DMA controllers. In such
cases, bus requests from the DMA controllers
have a higher priority than a request from an
external bus master.
The PHI pin is an output driven by the internal
system clock. It can be used by the system for
synchronization with the eZ80190 device.
Architectural Overview
21
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