ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 124

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
[7:0]
SRR
Bus Clock Speed
The I
mode).
To ensure correct detection of START and STOP conditions on the bus, the I
must sample the I
fastest master on the bus. The sampling frequency should therefore be at least 1
MHz (4 MHz in FAST mode) to guarantee correct operation with other bus mas-
ters.
The I
device system clock and the value in the I2Cx_CCR bits 2 to 0. The bus clock
speed generated by the I
the input clock and the values in I2Cx_CCR[2:0] and I2Cx_CCR[6:3].
I
The I2Cx_SRR register, indicated in
value to this register will perform a software reset of the I
2
C Software Reset Register
2
2
Value
00h–FFh Writing any value to this register performs a software reset of
C bus is defined for bus clock speeds up to 100 kbps (400 kbps in FAST
C sampling frequency is determined by the frequency of the eZ80190
W
X
7
Table 56. I
Description
the I
(I2C0_SRR = CDh, I2C1_SRR = DDh)
2
C bus at least ten times faster than the bus clock speed of the
W
X
6
2
C module.
2
2
C Software Reset Register
C in MASTER mode is determined by the frequency of
PRELIMINARY
W
X
5
W
X
4
Table
56, is a Write Only register. Writing any
W
X
3
W
X
2
2
C module.
W
1
X
I
2
C Serial I/O Interface
W
X
0
2
C
110