ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 155

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Name
DMA0_SAR_L
DMA0_SAR_H
DMA0_SAR_U
DMA0_DAR_L
DMA0_DAR_H
DMA0_DAR_U
DMA0_BC_L
DMA0_BC_H
DMA Interrupts
DMA Control Registers
When both channels are configured for CYCLE-STEAL mode, the 2 DMA chan-
nels alternate stealing execution cycles from the CPU. First, DMA Channel 0 per-
forms a cycle-steal single-byte transfer then releases the bus to the CPU for the
next 8 clock cycles. Then, DMA channel 1 requests the bus and gains access to
pass one of its bytes. After DMA channel 1 completes the transfer of its byte, con-
trol is returned to the CPU for another 8 clock cycles. This process repeats until
one or both of the DMA channels complete the transfer of all required bytes.
If DMA channel 0 is programmed in CYCLE-STEAL mode and DMA channel 1 is
programmed in BURST mode, DMA channel 1 is not allowed to transfer its data
until DMA channel 0 completes its entire transfer.
Each DMA controller can generate an interrupt request to the CPU when its mem-
ory transfer is complete. The DMA interrupts are enabled by setting bit 6 in the
DMA Control register (either DMA0_CTL or DMA1_CTL) to 1. The default opera-
tion is for the DMA interrupts to be disabled. Each DMA channel is capable of gen-
erating an interrupt when its 16-bit data byte transfer counter register reaches its
terminal count of
field in the DMA Control registers to disable the DMA channel that is generating
the input. Clearing the interrupt enable bit (DMAx_CTL[6] = IRQ_DMA) does not
clear the interrupt to the CPU after it is set.
Table 76
accessed by the CPU using I/O instructions.
Description
DMA0 Source Address Low Byte register
DMA0 Source Address High Byte register
DMA0 Source Address Upper Byte register
DMA0 Destination Address Low Byte register
DMA0 Destination Address High Byte register
DMA0 Destination Address Upper Byte register
DMA0 Byte Count Low Byte register
DMA0 Byte Count High Byte register
lists the control registers used by the DMA controller. These registers are
0000h
Table 76. DMA Registers
. The interrupts are cleared by resetting the DMA_EN bit
PRELIMINARY
eZ80190 Product Specification
Access
CPU
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Direct Memory Access Controller
Reset
Value
00h
00h
XX
XX
XX
XX
XX
XX
Register
Address
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
141