ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 61

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
GPIO Control Registers
Bit
Reset
CPU Access
Note: X = Undefined; R/W = Read/Write.
Edge-Triggered Interrupts
When the port is configured for edge-triggered interrupts, the corresponding port
pin is tristated. If the pin receives the correct edge from an external device, the
port pin generates an interrupt request signal to the CPU. Any time a port pin is
configured for edge-triggered interrupt, writing a 1 to that pin’s Port x Data register
causes a reset of the edge-triggered interrupt. The programmer must set the bit in
the Port x Data register to 1 before entering either single- or dual-edge-triggered
interrupt mode for that port pin.
When configured for dual-edge-triggered interrupt mode (GPIO Mode 6), both a
rising and a falling edge on the pin cause an interrupt request to be sent to the
CPU.
When configured for single-edge-triggered interrupt mode (GPIO Mode 9), the
value in the Port x Data register determines if a positive or negative edge causes
an interrupt request. A 0 in the Port x Data register bit sets the selected pin to gen-
erate an interrupt request for falling edges. A 1 in the Port x Data register bit sets
the selected pin to generate in interrupt request for rising edges.
The 16 GPIO Control Registers operate in groups of 4 with a set for each Port (A,
B, C, and D). Each GPIO port features a Port Data register, Port Data Direction
register, Port Alternate register 1, and Port Alternate register 2.
Port x Data Registers
When the port pins are configured for one of the output modes, the data written to
the Port x Data registers, detailed in
pins. In all modes, reading from the Port x Data registers always returns the cur-
rent sampled value of the corresponding pins. When the port pins are configured
as edge-triggered interrupt sources, writing a 1 to the corresponding bit in the Port
x Data register clears the interrupt signal that is sent to the CPU. When the port
pins are configured for edge-selectable interrupts or level-sensitive interrupts, the
value written to the Port x Data register bit selects the interrupt edge or interrupt
level. See
(PA_DR = 96h, PB_DR = 9Ah, PC_DR = 9Eh, PD_DR = A2h)
Table 12
R/W
X
7
Table 13. Port x Data Registers
on page 44 for more information.
R/W
X
6
PRELIMINARY
R/W
X
5
Table
R/W
X
4
13, are driven on the corresponding
R/W
X
3
eZ80190 Product Specification
R/W
X
2
General-Purpose Input/Output
R/W
X
1
R/W
X
0
47