ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 108

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Clk1 Signal
Clk2 Signal
SCL Signal
Arbitration
A master may start a transfer only if the bus is free. Two or more masters may
generate a START condition within the minimum hold time of the START condi-
tion. The result is a defined START condition to the bus. Arbitration occurs on the
SDA line while the SCL line is at the High level in such a way that the master,
(which transmits a High level while another master is transmitting a Low level),
switches off its data output stage. The master switches off its data output stage
because the level on the bus does not correspond to its own level.
Arbitration can continue for many bits. Its first stage is a comparison of the
address bits. If the masters are each trying to address the same device, arbitration
continues with a comparison of the data. Because address and data information
on the I
master which loses the arbitration can generate clock pulses until the end of the
byte in which it loses the arbitration.
If a master also incorporates a slave function and it loses arbitration during the
addressing stage, it is possible that the winning master is trying to address it. The
losing master must switch over immediately to SLAVE RECEIVE mode.
illustrates the arbitration procedure for two masters. Of course, more may be
involved (depending on how many masters are connected to the bus). The
moment there is a difference between the internal data level of the master gener-
ating DATA 1 and the actual level on the SDA line, its data output is switched off,
which means that a High output level is then connected to the bus. As a result, the
data transfer initiated by the winning master is not affected. Because control of the
I
there is no central master, nor any order of priority on the bus.
Special attention must be paid if, during a serial transfer, the arbitration procedure
is still in progress at the moment when a repeated START condition or a STOP
condition is transmitted to the I
2
C bus is decided solely on the address and data sent by competing masters,
2
C bus is used for arbitration, no information is lost during this process. A
Figure 20. Clock Synchronization In I
Counter
Reset
PRELIMINARY
2
Wait State
C bus. If it is possible for such a situation to occur,
2
C Protocol
Start Counting
High Period
I
2
C Serial I/O Interface
Figure 20
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