ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 32

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Pin # Symbol
78
79
80
PD2
SCK0
RTS0
PD3
SS0
CTS0
PD4
DTR0
Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued)
Function
GPIO Port D
SPI Serial
Clock
Request to
Send
GPIO Port D
Slave Select
Clear to Send Input, Active Low
GPIO Port D
Data Terminal
Ready
Signal Direction
Input/Output
Input/Output
Output, Active Low The RTS0 pin carries the modem-control signal
Input/Output
Input, Active Low
Input/Output
Output, Active Low The DTR0 pin carries the modem control signal to
PRELIMINARY
Description
The PD2 pin can be used for general-purpose I/
O. It can be individually programmed as an input
or output and can also be used individually as an
interrupt input. Each Port D pin, when
programmed as an output, can be selected to be
an open-drain or open-source output. Port D is
multiplexed with one channel of the UZI interface.
The SPI serial clock signal is multiplexed with
PD2.
from the UART. This signal is multiplexed with
PD2.
The PD3 pin can be used for general-purpose I/
O. It can be individually programmed as an input
or output and can also be used individually as an
interrupt input. Each Port D pin, when
programmed as an output, can be selected to be
an open-drain or open-source output. Port D is
multiplexed with one channel of the UZI interface.
The slave select input line is used to select a
slave device in SPI mode. This signal is
multiplexed with PD3.
The CTS0 pin carries the modem status signal to
the UART. This signal is multiplexed with PD3.
The PD4 pin can be used for general-purpose I/
O. It can be individually programmed as an input
or output and can also be used individually as an
interrupt input. Each Port D pin, when
programmed as an output, can be selected to be
an open-drain or open-source output. Port D is
multiplexed with one channel of the UZI interface.
the UART. This signal is multiplexed with PD4.
Architectural Overview
18