ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 107

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

eZ80190 Product Specification
93
Data Output by Transmitter
Data Output by Receiver
SCL Signal From Master
1
2
8
9
S
Start Condition
Clock Pulse for Acknowledge
2
Figure 19. I
C Acknowledge
Clock Synchronization
All masters generate their own clocks on the SCL line to transfer messages on the
2
I
C bus. Data is only valid during the High period of each clock.
2
Clock synchronization is performed using the wired AND connection of the I
C
interfaces to the SCL line, meaning that a High-to-Low transition on the SCL line
causes the relevant devices to start counting from their Low period. When a
device clock goes Low, it holds the SCL line in that state until the clock High state
is reached. See
Figure
20. The Low-to-High transition of this clock, however, may
not change the state of the SCL line if another clock still exists within its Low
period. The SCL line is held Low by the device with the longest Low period.
Devices with shorter Low periods enter a High WAIT state during this time.
When all devices complete counting off their Low periods, the clock line goes
High. There is no difference between the device clocks and the state of the SCL
line; therefore, all of the devices begin counting their High periods. The first device
to complete its High period again pulls the SCL line Low. In this way, a synchro-
nized SCL clock is generated with its Low period determined by the device with
the longest clock Low period, and its High period determined by the device with
the shortest clock High period.
2
PS006613-0306
PRELIMINARY
I
C Serial I/O Interface