ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 98

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
(CPHA bit = 0) Data Out
(CPHA bit = 1) Data Out
Sample Input
Sample Input
SCK (CPOL bit = 0)
SCK (CPLO bit = 1)
SPI Functional Description
SS (To Slave)
CPHA
0
0
1
1
master and slave must operate with the same timing. The master device always
places data on the MOSI line a half-cycle before the clock edge (SCK signal), for
the slave device to latch the data.
Figure 15
When a master device transmits to a slave device via the MOSI signal, the slave
device responds by sending data to the master via the master’s MISO signal. The
result is a full-duplex transmission, with both data out and data in synchronized
Table 38. SPI Clock Phase and Clock Polarity Operation
CPOL
illustrates a block diagram of the serial peripheral interface circuitry.
0
1
0
1
MSB
MSB
1
6
Transmit
Figure 14. SPI Timing
Falling
Falling
Rising
Rising
Edge
SCK
6
2
PRELIMINARY
5
Number of Cycles on the SCK Signal
5
3
Receive
4
Falling
Falling
Rising
Rising
Edge
SCK
4
4
3
3
5
eZ80190 Product Specification
Idle State
SCK
High
High
Low
Low
2
2
6
1
Serial Peripheral Interface
Characters?
1
Between
SS High
7
Yes
Yes
LSB
No
No
8
LSB
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