ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 113

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Code
48h
38h
68h
78h
B0h
Note: R = Read bit. The lsb is set to 1.
I
Addr + R transmitted,
ACK not received
Arbitration lost
Arbitration lost,
SLA+W received, ACK
transmitted
Arbitration lost,
General call addr
received, ACK
transmitted
Arbitration lost, SLA+R
received, ACK
transmitted
2
If 10-bit addressing is being used, the slave is first addressed using the full 10-bit
address plus the Write bit. The master then issues a restart followed by the first
part of the 10-bit address again, but with the READ bit. The status code is then
40h
If a repeated START condition is received, the status code is
After each data byte is received, the IFLG is set and one of the status codes listed
in
C State
Table 47
or
Table 46. I
48h
. The slave remains selected prior to the restart.
is contained in the I2Cx_SR register.
2
C Master Receive Status Codes (Continued)
Microprocessor Response
For a 7-bit address: set STA,
clear IFLG
Or set STP, clear IFLG
Or set STA & STP, clear IFLG Transmit STOP then
For a 10-bit address: Write
extended address byte to
DATA, clear IFLG
Clear IFLG
Or set STA, clear IFLG
Clear IFLG, clear ACK = 0
Or clear IFLG, set ACK = 1
Same as code 68h
Write byte to DATA, clear
IFLG, clear ACK = 0
Or write byte to DATA, clear
IFLG, set ACK = 1
PRELIMINARY
Next I
Transmit repeated
START
Transmit STOP
START
Transmit extended
address byte
Return to the IDLE state
Transmit START when
bus is free
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Same as code 68h
Transmit last byte,
receive ACK
Transmit data byte,
receive ACK
2
C Action
10h
I
2
C Serial I/O Interface
instead of
08h
.
99