ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 94

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
DCD
6
RI
5
DSR
4
CTS
3
DDCD
2
TERI
1
DDSR
0
DCTS
UART Modem Status Registers
The UART Modem Status Registers, indicated in
status of the UART signals.
Value
0–1
0–1
0–1
0–1
0–1
0–1
0–1
0–1
(UART0_MSR = C6h, UART1_MSR = D6h)
Table 36. UART Line Status Registers
Description
Data Carrier Detect
In NORMAL mode, this bit reflects the inverted state of the
DCDx input pin. In LOOP-BACK mode, this bit reflects the
value of the UARTx_MCTL[3] = OUT2.
Ring Indicator
In NORMAL mode, this bit reflects the inverted state of the RIx
input pin. In LOOP-BACK mode, this bit reflects the value of
the UARTx_MCTL[2] = OUT1.
Data Set Ready
In NORMAL mode, this bit reflects the inverted state of the
DSRx input pin. In LOOP-BACK mode, this bit reflects the
value of the UARTx_MCTL[0] = DTR.
Clear to Send
In NORMAL mode, this bit reflects the inverted state of the
CTSx input pin. In LOOP-BACK mode, this bit reflects the
value of the UARTx_MCTL[1] = RTS.
Delta Status Change of DCD
This bit is set to 1 whenever the DCDx pin changes state. This
bit is reset to 0 when the UARTx_MSR register is read.
Trailing Edge Change on RI
This bit is set to 1 whenever a falling edge is detected on the
RIx pin. This bit is reset to 0 when the UARTx_MSR register is
read.
Delta Status Change of DSR
This bit is set to 1 whenever the DSRx pin changes state. This
bit is reset to 0 when the UARTx_MSR register is read.
Delta Status Change of CTS
This bit is set to 1 whenever the CTSx pin changes state. This
bit is reset to 0 when the UARTx_MSR register is read.
X
R
7
X
R
6
PRELIMINARY
X
R
5
R
X
4
Universal Asynchronous Receiver/Transmitter
R
X
3
eZ80190 Product Specification
Table
R
X
2
36, are used to show the
R
X
1
X
R
0
80