ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 123

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Bit
Reset
CPU Access
Note: W = Read Only.
Bit
Position
7
[6:3]
M
[2:0]
N
Only I2Cx_CCR registers share the same I/O addresses as the Read Only
I2Cx_SR registers.
The I
a frequency of f
f
In MASTER mode, the I
The use of two separately-programmable dividers allows the MASTER mode out-
put frequency to be set independently of the frequency at which the I
sampled. These dividers are particularly useful in multimaster systems because
the I
fastest master on the bus to ensure that START and STOP conditions are always
detected. By using two programmable clock divider stages, a high sampling fre-
quency can be ensured, while allowing the MASTER mode output to be set to a
lower frequency.
samp
2
2
C bus sampling frequency must be at least 10 times the frequency of the
in the following equation.
f
C clocks are derived by the eZ80190 device’s system clock, which provides
SAMP
f
SCL
Value
0
0000–
1111
000–111 I
=
=
Table 55. I
(I2C0_CCR = CCh, I2C1_CCR = DCh)
sclk
f
10 x (M+1) x 2
SCLK
2
W
Description
Reserved.
I
7
0
2
2
N
. The I
C clock divider scalar value.
C clock divider exponent.
f
SCLK
2
W
C clock output frequency on SCLx (f
2
2
6
0
C Clock Control Registers
C bus is sampled by the I
PRELIMINARY
N
W
5
0
W
4
0
W
3
0
2
C block at the frequency
W
2
0
scl
W
1
0
I
) is provided by:
2
C Serial I/O Interface
2
W
C bus is
0
0
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