ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 36

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

Register Map
PS006613-0306
Address
(hex)
Programmable Reload Counter/Timers
80
81
82
83
84
85
86
87
Notes:
1. After an external pin reset, the Watch-Dog Timer Control register resets to 00h. After a Watch-Dog Timer time-
2. When the CPU reads this register, the pin value of the port is read.
out reset, the Watch-Dog Timer Control register resets to 20h.
Mnemonic
TMR0_CTL
TMR0_DR_L
TMR0_RR_L
TMR0_DR_H
TMR0_RR_H
TMR1_CTL
TMR1_DR_L
TMR1_RR_L
TMR1_DR_H
TMR1_RR_H
TMR2_CTL
TMR2_DR_L
TMR2_RR_L
Note:
All on-chip peripheral registers are accessed in the I/O address space. All I/O
operations employ 16-bit addresses. The upper byte of the 24-bit address bus is
forced to
using 16-bit addresses within the range of
peripherals; where
not generated if the address space programmed for the I/O Chip Selects overlap
the
80h
Registers at unused addresses within the
on-chip peripherals are not implemented. READ access to such addresses
return unpredictable values and WRITE access produces no effect.
Table 2
to
00h
FFh
(ADDR[23:16] =
address range.
Name
Timer 0 Control Register
Timer 0 Data Register—Low Byte
Timer 0 Reload Register—Low Byte
Timer 0 Data Register—High Byte
Timer 0 Reload Register—High Byte
Timer 1 Control Register
Timer 1 Data Register—Low Byte
Timer 1 Reload Register—Low Byte
Timer 1 Data Register—High Byte
Timer 1 Reload Register—High Byte
Timer 2 Control Register
Timer 2 Data Register—Low Byte
Timer 2 Reload Register—Low Byte
diagrams the register map for the eZ80190 device.
xx
is any value from
Table 2. Register Map
PRELIMINARY
00h
) during all I/O operations. All I/O operations
00h
80h
to
to
FFh
eZ80190 Product Specification
FFh
80h
. External I/O Chip Selects are
are routed to the on-chip
to
Reset
FFh
(hex)
00
00
00
00
00
00
00
00
00
00
00
00
00
range assigned to
Access
CPU
R/W
R/W
R/W
W
W
W
W
W
R
R
R
R
R
Register Map
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