ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 154

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
BUSREQ
BUSACK
DMA
write
DMA
read
CLK
DMA Transfer Modes
DMA Channel Priorities
From Source Address
There are two modes of operation for the DMA channels. The DMA can transfer
data in BURST mode or CYCLE-STEAL mode. The data transfer mode is con-
trolled by the BURST bit in the DMA Control registers (DMAx_CTL[4]).
In BURST mode, the DMA controller takes control of the bus within the eZ80190
device for the entire time period required to complete the data transfer. The CPU
is idled while the DMA controller completes its BURST mode data transfer.
The default operation for the DMA controller is CYCLE-STEAL mode in which the
DMA controller requests and then gains access to the bus for the transfer of only
one byte at a time. After the transfer of each byte, the DMA returns control of the
bus back to the CPU. The DMA then waits for the CPU to complete 8 clock cycles
before again requesting control of the bus. As a result, other activities can pro-
ceed while the DMA is transferring data in the background. CYCLE-STEAL mode
slows down the processing of the main program task of the CPU. See
In all operating mode combinations, DMA Channel 0 is prioritized higher than
DMA Channel 1. If Channel 0 is configured for BURST mode operation, Channel 0
completes its entire block transfer before Channel 1 begins its transfer.
DMA Reads Data
Current Instruction
eZ80
To Destination Address
DMA Writes Data
®
DMA Initiates
Bus Request
Completes
Figure 25. DMA CYCLE-STEAL Timing
eZ80
Bus to DMA
PRELIMINARY
®
Releases
In Cycle-Steal Mode, DMA will Request
Bus to eZ80
1
DMA Returns
the Bus Again on the 8th Clock Cycle
Following Return of the Bus
2
3
®
eZ80190 Product Specification
4
New Bus Request
eZ80
DMA Initiates
Direct Memory Access Controller
Return of the Bus
5
®
Acknowledges
6
7
8
Figure
25.
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