ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 75

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Baud Rate Generator
See
and
tion of the UZI Baud Rate Generator and the UZI control registers appear in this
chapter.
The Baud Rate Generator (BRG) is located within the UZI, but outside the three
serial communication controllers. The Baud Rate Generator creates a lower fre-
quency clock from the high-frequency system clock provided as an input to each
UZI. Baud Rate Generator output is used as the clock source by the SPI and the
UART. The I
Baud Rate Generator Functional Description
The Baud Rate Generator consists of a 16-bit downcounter, two registers, and
associated decoding logic. The Baud Rate Generator’s initial value is defined by
the two BRG Divisor Latch registers, {BRGx_DLR_H, BRGx_DLR_L}. At the rising
edge of each system clock, the BRG decrements until it reaches the value
On the next system clock rising edge, the BRG reloads the initial value from
{BRGx_DLR_H, BRGx_DLR_L) and outputs a pulse to indicate the end-of-count.
Calculate the BRG output frequency with the following equation:
Upon RESET, the 16-bit BRG divisor value resets to
sor value of
Write to either the Low- or High-byte registers for the BRG Divisor Latch causes
both the Low and High bytes to load into the BRG counter, and causes the count
to restart.
The divisor registers can only be accessed if bit 7 of the UART Line Control regis-
ter (UARTx_LCTL) is set to 1. After reset, this bit is reset to 0.
Recommended Usage of the Baud Rate Generator
The following is the normal sequence of operations that should occur after the
eZ80190 device is powered on to configure the UZI Baud Rate Generator:
•
•
•
•
Assert and deassert RESET
Set UARTx_LCTL[7] to 1 to enable access of the BRG divisor registers
Program the BRGx_DLR_L and BRGx_DLR_H registers
Clear UARTx_LCTL[7] to 0 to disable access of the BRG divisor registers.
I
Serial Peripheral
2
BRGx Output Frequency =
C Serial I/O Interface
2
0001h
C device generates its timing directly from the primary system clock.
is also valid, and effectively bypasses the BRG. A software
Interface,
PRELIMINARY
chapters for detailed operating information. A descrip-
Universal Asynchronous
{BRGx_DLR_H, BRGx_DLR_L}
System Clock Frequency
0002h
Receiver/Transmitter,
. A minimum BRG divi-
Universal ZiLOG Interface
0001h
.
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