ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 87

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:6]
FSTS
[5:4]
[3:1]
INSTS
0
INTBIT
UART Interrupt Identification Register
The Read Only UART Interrupt Identification register, indicated in
the user to check the status of interrupts and whether the FIFO is enabled. These
registers share the same I/O addresses as the UARTx_FCTL registers. Status
codes for the UARTx_IIR register are provided in
INSTS
Value
011
010
110
001
000
Value
00
11
00
000–
110
0
1
Table 29. UART Interrupt Identification Registers
Table 30. UART Interrupt Status Codes
(UART0_IIR = C2h, UART1_IIR = D2h)
Description
FIFO is disabled.
FIFO is enabled.
Reserved
Interrupt Status Code
The code indicated in these three bits is valid only if the
interrupt bit is 1. If two internal interrupt sources are active
and their respective enable bits are High, only the higher
priority interrupt is seen by the application. The lower priority
interrupt code is indicated only after the higher priority
interrupt is serviced.
There is an active interrupt source within the UART.
There is not an active interrupt source within the UART.
R
Priority
Highest
Second
Third
Fourth
Lowest
7
0
R
6
0
PRELIMINARY
Interrupt Type
Receiver Line Status
Receive Data Ready or Trigger Level
Character Time-out
Transmit Buffer Empty
Modem Status
R
5
0
Table 30
R
4
0
Universal Asynchronous Receiver/Transmitter
lists interrupt status codes.
R
3
0
eZ80190 Product Specification
Table
R
2
0
30.
R
1
0
Table
R
0
1
29, allows
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