ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 54

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Watch-Dog Timer Operation
Watch-Dog Timer Registers
Enabling And Disabling The WDT
The Watch-Dog Timer is disabled upon a system RESET. To enable the WDT, the
application program must set the WDT_EN bit (bit 7) of the WDT_CTL register.
When enabled, the WDT cannot be disabled without a system RESET.
Time-Out Period Selection
There are four choices of time-out periods for the WDT—2
system clock cycles. With a 50-MHz crystal oscillator, the available WDT time-out
periods are approximately 5.24 ms, 83.9 ms, 671 ms, and 2.68 s. The WDT time-
out period is defined by the WDT_PERIOD field of the WDT_CTL register
(WDT_CTL[1:0]).
RESET Or NMI Generation
Upon a WDT time-out, the RST_FLAG bit in the WDT_CTL register is set to 1. In
addition, the WDT can cause a system RESET or send a nonmaskable interrupt
(NMI) signal to the CPU. The default operation is for the WDT to cause a system
RESET. The reset pulse generated by a Watch-Dog Timer time-out is 64 clock
cycles wide. It asserts/deasserts on the rising edge of the clock. The RST_FLAG
bit can be polled by the CPU to determine the source of the RESET event.
If the NMI_OUT bit in the WDT_CTL register is set to 1, then upon time-out, the
WDT asserts an NMI for CPU processing. The RST_FLAG bit can be polled by
the CPU to determine the source of the NMI event.
Watch-Dog Timer Control Register
The Watch-Dog Timer Control register, detailed in
register used to enable the Watch-Dog Timer, set the time-out period, indicate the
source of the most recent RESET, and select the required operation upon WDT
time-out.
PRELIMINARY
eZ80190 Product Specification
Table
10, is an 8-bit Read/Write
18
, 2
22
, 2
Watch-Dog Timer
25
, and 2
27
40