ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 112

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Code
38h
Code
40h
Note: R = Read bit. The lsb is set to 1.
Table 45. I
I
Arbitration lost
I
Addr + R transmitted,
ACK received
2
2
When all bytes are transmitted, the microprocessor should write a 1 to the Master
Mode Stop bit (STP) bit in the I2Cx_CTL register. The I
condition, clears the STP bit, and returns to the IDLE state.
Master Receive
In MASTER RECEIVE mode, the I
transmitter.
After the START condition is transmitted, the IFLG bit is set to 1 and the status
code
loaded with the slave address (or the first part of a 10-bit slave address), with the
lsb set to 1 to signify a READ. The IFLG bit should be cleared to 0 as a prompt for
the transfer to continue.
When the 7-bit slave address (or the first part of a 10-bit address) and the read bit
are transmitted, the IFLG bit is set and one of the status codes listed in
contained in the I2Cx_SR register.
C State
C State
08h
2
C Master Transmit Status Codes For Data Bytes (Continued)
is loaded in the I2Cx_SR register. The I2Cx_DR register should be
Table 46. I
Microprocessor Response
Clear IFLG
Or set STA, clear IFLG
Microprocessor Response
For a 7-bit address, clear IFLG,
ACK = 0
Or clear IFLG, ACK = 1
For a 10-bit address, write
extended address byte to
DATA, clear IFLG
2
C Master Receive Status Codes
PRELIMINARY
2
C receives a number of bytes from a slave
Next I
Return to the IDLE state
Transmit START when
bus free
Next I
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Transmit extended
address byte
2
C then transmits a STOP
2
2
C Action
C Action
I
2
C Serial I/O Interface
Table 46
is
98