ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 76

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
UZI and BRG Control Registers
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
[7:2]
[1:0]
UZI_MODE
UZI Control Registers
The UZI Control registers select between the three available serial communication
controllers: I
device features its own UZI Control register.
BRG Divisor Latch Registers—Low Byte
This register holds the Low byte of the 16-bit divisor count loaded by the proces-
sor for baud rate generation. The 16-bit clock divisor value is returned by
{BRGx_DLR_H, BRGx_DLR_L}, where x is either 0 or 1 to identify the two avail-
able UZI devices. Upon RESET, the 16-bit BRG divisor value resets to
initial 16-bit divisor value must be between
and
BRG clock divisor ratio is 2.
A write to either the Low or High byte registers for the BRG Divisor Latch causes
both bytes to be loaded into the BRG counter and the count restarted.
Bit 7 of the associated UART Line Control register (UARTx_LCTL) must be set to
1 to access this register for each UZI device. See
(UARTx_LCTL) on page 75 for more information.
The BRGx_DLR_L registers share the same address space with the UARTx_RBR
and UARTx_THR registers. Bit 7 of the associated UART Line Control register
(UARTx_LCTL) must be set to 1 to enable access for this register within each UZI
device.
0001h
Value
000000 Reserved
00
01
10
11
are invalid and proper operation is not guaranteed. Thus the minimum
2
C, SPI and UART. Each of the two UZI devices on the eZ80190
Description
All UZI devices are disabled.
UART is enabled.
SPI is enabled.
I
(UZI0_CTL = CFh, UZI1_CTL = DFh)
2
R
7
0
C is enabled.
Table 23. UZI Control Registers
R
6
0
PRELIMINARY
R
5
0
R
4
0
0002h
R
3
0
and
UART Line Control Register
FFFFh
R
2
0
Universal ZiLOG Interface
as the values
R/W
1
0
R/W
0002h
0
0
0000h
. The
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