ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 106

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
SDA Signal
SCL Signal
Start Condition
cant bit (msb) first. See
the transmitter into a WAIT state. Data transfer then continues when the receiver
is ready for another byte of data and releases SCL.
Acknowledge
Data transfer with an ACK function is obligatory. The ACK-related clock pulse is
generated by the master. The transmitter releases the SDA line (High) during the
ACK clock pulse. The receiver must pull down the SDA line during the ACK clock
pulse so that it remains Low during the High period of this clock pulse. See
Figure
A receiver that is addressed is obliged to generate an ACK after each byte is
received. When a slave receiver does not acknowledge the slave address (that is,
the slave receiver is unable to receive because it is performing some real-time
function), the data line must be left High by the slave. The master then generates
a STOP condition to abort the transfer.
If a slave receiver acknowledges the slave address, but cannot receive any more
data bytes, the master must abort the transfer. The abort is indicated by the slave
generating the Not Acknowledge (NACK) on the first byte to follow. The slave
leaves the data line High and the master generates the STOP condition.
If a master receiver is involved in a transfer, it must signal the end of the data
transfer to the slave transmitter by not generating an ACK on the final byte
clocked out of the slave. The slave transmitter must release the data line to allow
the master to generate a STOP or a repeated START condition.
S
19.
MSB
1
Figure 18. I
2
Figure
PRELIMINARY
Acknowledge
From Receiver
2
8
C Frame Structure
18. A receiver can hold the SCL line Low to force
9
Clock Line Held Low By Receiver
1
Acknowledge
From Receiver
ACK
9
I
2
C Serial I/O Interface
Stop Condition
P
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