ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 121

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:3]
STAT
[2:0]
Code
00h
08h
10h
18h
20h
28h
30h
38h
40h
I
The I2Cx_SR register, indicated in
a 5-bit status code in the five most significant bits. The three least significant bits
are always 0. The Read Only I2Cx_SR registers share the same I/O addresses as
the Write Only I2Cx_CCR registers.
There are 29 possible status codes, indicated in
register contains the status code
no interrupt is generated and the IFLG bit in the I2Cx_CTL register is not set. All
other status codes correspond to a defined state of the I
When the device enters each of these states, the corresponding status code
appears in this register and the IFLG bit in the I2Cx_CTL register is set. When the
IFLG bit is cleared, the status code returns to
2
C Status Register
Status
Bus error
START condition transmitted
Repeated START condition transmitted
Address + write bit transmitted, ACK received
Address + write bit transmitted, ACK not received
Data byte transmitted in MASTER mode, ACK received
Data byte transmitted in MASTER mode, ACK not received
Arbitration lost in address or data byte
Address + read bit transmitted, ACK received
000
Value
00000–
11111
(I2C0_SR = CCh, I2C1_SR = DCh)
Description
5-bit I
Reserved.
R
7
1
Table 53. I
Table 54. I
2
C status code.
R
6
1
PRELIMINARY
2
C Status Registers
2
C Status Codes
R
5
1
F8h
Table
, no relevant status information is available,
R
4
1
53, is a Read Only register that contains
F8h
R
3
1
Table
.
54. When the I2Cx_SR
R
2
0
2
C.
R
1
0
I
2
C Serial I/O Interface
R
0
0
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