ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 178

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
ZDI_ACTIVE
6
RESET_PEND
5
HALT
4
ADL
3
MADL
2
IEF1
[1:0]
ZDI Status Register
The ZDI Status register, indicated in
eZ80190 device and the CPU.
ZDI Read Register Low, High, and Upper
The ZDI register Read Only address space offers Low, High, and Upper functions,
which contain the value read by a read operation from the ZDI Read/Write Control
register (ZDI_RW_CTL). This data is valid only while in ZDI BREAK mode and
only if the instruction is read by a request from the ZDI Read/Write Control regis-
ter. See
(ZDI_STAT = 03h in the ZDI Register Read Only Address Space)
Table
Value Description
0
1
0
1
0
1
0
1
0
1
0
1
00b
93.
R
7
0
Table 92. ZDI Status Register
The CPU is not functioning in ZDI mode.
The CPU is currently functioning in ZDI mode.
No RESET event is currently in progress.
A RESET event is in progress.
eZ80190 is not currently in HALT mode.
eZ80190 is currently in HALT mode.
The CPU is operating in Z80 MEMORY mode (ADL bit
flag = 0).
The CPU is operating in ADL MEMORY mode (ADL bit
flag = 1).
The CPU’s Mixed-Memory mode (MADL) bit is reset to 0.
The CPU’s Mixed-Memory mode (MADL) bit is set to 1.
The CPU’s Interrupt Enable Flag 1 is reset to 0. Maskable
interrupts are disabled.
The CPU’s Interrupt Enable Flag 1 is set to 1. Maskable
interrupts are enabled.
Reserved—must be 0.
R
6
0
PRELIMINARY
R
5
0
Table
R
4
0
92, provides current information on the
R
3
0
eZ80190 Product Specification
R
2
0
R
1
0
ZiLOG Debug Interface
R
0
0
164