tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 196

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14. 8-bit Timer Counter (TC0)
RA002
T001CR<T00RUN>
T00MOD<TFF0>
Source clock
Counter
Write to T00PWM
Double buffer
T00PWM
<PWMAD>
T00PWM
<PWMDUTY>
PWM0 pin output
INTT00 interrupt
request
flow occurs and the up counter is cleared to "0x00". At the same time, the output of the
reversed. When T00MOD<TFF0> is "0", the
T00MOD<TFF0> is "1", the
at this time, an INTT00 interrupt request is generated. (No interrupt request is generated at the 2 u n-th -1
overflow.) Subsequently, the up counter continues counting up.
cleared to "0x00". The
(Example)
Subsequently, the up counter continues counting up. When the up counter value reaches 128, an over-
When T001CR<T00RUN> is set to "0" during the timer operation, the up counter is stopped and
Becomes the level selected at
TFF0 while the timer is stopped
Write m
m
m
Operate TC00 in the 8-bit PWM mode with the operation clock of fcgck/2 and output a duty pulse nearly equivalent to 11.6
Ps (fcgck = 10 MHz)
(Actually, output a total duty pulse of 23.2 Ps in 2 cycles (102.4 Ps))
SET
SET
LD
DI
SET
EI
LD
LD
SET
Timer start
(Duty pulse)
Figure 14-6 8-bit PWM Mode Timing Chart
0
m
1
128 counts
(Cycle 1)
When the double buffer is enabled (T00MOD<DBE0>=”1”)
(P7FC).0
(P7CR).0
(POFFCR0),0x10
(EIRH).4
(T00MOD),0xF2
(T00PWM),0x73
(T001CR).0
PWM0
Match detection
m
Write r
m+1
r
PWM0
pin returns to the level selected at T00MOD<TFF0>.
(Duty pulse)
Overflow
128
Counter
clear
No interrupt request
is generated
0
pin changes from the "L" to "H" level. If the 2 u n-th overflow occurs
m
128 counts
1
(Cycle 2)
Page 182
Match detection
m
; Sets P7FC0 to "1"
; Sets P7CR0 to "1"
; Sets TC001EN to "1"
; Sets the interrupt master enable flag to "disable"
; Sets the INTTC00 interrupt enable register to "1"
; Sets the interrupt master enable flag to "enable"
; Selects the 8-bit PWM mode and fcgck/2
; Sets the timer register (duty pulse)
; (11.6Ps u 2) / (2/fcgck) = 0x73
; Starts TC00
m+1
PWM0
(Duty pulse)
128
Overflow
Counter
clear
Reflected by an
interrupt request
Interrupt request
0
r
r
pin changes from the "H" to "L" level. When
1
128 counts
(Cycle 3)
Write s
s
Match detection
r
r+1
128
Overflow
(Duty pulse)
Counter
clear
No interrupt request
is generated
0
128 counts
1
r+1
(Cycle 4)
Additional pulse
Match detection
r
Timer stop
r+1
128
TMP89FM42
s
Counter
clear
Reflected by an
interrupt request
Returns to the
level selected
at TFF0
0
PWM0
1
0
pin is