tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 48

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.3 System clock controller
2. CPU Core
RA001
• Start the IDLE0 and SLEEP0 modes
• Release the IDLE0 and SLEEP0 modes
mode. These modes are selected at the interrupt master enable flag (IMF), the individual inter-
rupt enable flag (EF5) for the time base timer and TBTCR<TBTEN>. After releasing the
IDLE0 or SLEEP0 mode, SYSCR2<TGHALT> is automatically cleared to "0" and the opera-
tion mode is returned to the mode preceding the IDLE0 or SLEEP0 mode. If
TBTCR<TBTEN> has been set at "1", the INTTBT interrupt latch is set.
reset and a reset by the voltage detection circuits. When a reset is released, the warm-up starts.
After the warm-up is completed, the NORMAL1 mode becomes active.
(Normal release mode)
Stop (disable) the peripherals such as a timer counter.
To start the IDLE0 or SLEEP0 mode, set SYSCR2<TGHALT> to "1".
The IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release
The IDLE0 and SLEEP0 modes are also released by a reset by the
Figure 2-11 IDLE0 and SLEEP0 Modes
No
"0"
No
No
Execution of the instruction
which follows the IDLE0 or
Starting IDLE0 or SLEEP0
Stopping peripherals by
mode by an instruction
SLEEP0 mode start
CPU and WDT stop
Interrupt processing
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TBTCR<TBTEN>
TBT source clock
TBT interrupt
instructions
Reset input
instruction
falling edge
IMF = "1"
enabled
No
Yes
Yes
"1"
Yes
(Interrupt release mode)
Yes
Reset
RESET
pin, a power-on
TMP89FM42