tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 50

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.3 System clock controller
2. CPU Core
RA001
PINTWUC:
VINTWUC:
Example 1: Switching from the NORMAL2 mode to the SLOW1 mode (when fc is used as the basic clock for the high-fre-
Example 2: Switching to the SLOW1 mode after the stable oscillation of the low-frequency clock oscillation circuit is con-
(2)
warm-up counter that the oscillation of the basic clock for the high-frequency clock has stabilized,
and then clear SYSCR2<SYSCK> to "0".
the main system clock (fm) is switched to fcgck.
turn off the low-frequency clock oscillator.
voltage detection circuits. When a reset is released, the warm-up starts. After the warm-up is com-
pleted, the NORMAL1 mode becomes active.
Switching from the SLOW1 mode to the NORMAL1 mode
Set SYSCR2<XEN> to "1" to enable the high-frequency clock (fc) to oscillate. Confirm at the
When a maximum of 8/fs + 2.5/fcgck [s] has elapsed since SYSCR2<SYSCK> is cleared to "0",
After switching, wait for 2 machine cycles or longer, and then clear SYSCR2<XTEN> to "0" to
The SLOW mode is also released by a reset by the
Note 1: Be sure to follow this procedure to switch the operation from the SLOW1 mode to the
Note 2: After switching SYSCR2<SYSCK>, be sure to wait for 2 machine cycles or longer before clear-
Note 3: When the main system clock (fm) is switched, the gear clock (fcgck) is synchronized with the
Note 4: When P0FC0 is "0", setting SYSCR2<XEN> to "1" causes a system clock reset.
Note 5: When SYSCR2<XEN> is set at "1", writing "1" to SYSCR2<XEN> does not cause the warm-up
SET
NOP
NOP
CLR
; #### Initialize routine ####
SET
LD
LD
SET
SET
; #### Interrupt service routine of warm-up counter interrupts ####
SET
NOP
NOP
CLR
RETI
DW
quency clock)
firmed at the warm-up counter (fs=32.768KHz, warm-up time = about 100 ms)
¦
¦
¦
¦
NORMAL1 mode.
ing SYSCR2<XTEN> to "0". Clearing it within 2 machine cycles causes a system clock reset.
clock that is a quarter of the basic clock (fs) for the low-frequency clock. For the synchronization,
fm is stopped for a period of 2.5/fcgck [s] or shorter.
counter to start counting the source clock.
(SYSCR2).4
(SYSCR2).6
(P0FC).2
(WUCCR), 0x02
(WUCDR), 0x33
(EIRL).4
(SYSCR2).5
(SYSCR2).4
(SYSCR2).6
PINTWUC
Page 36
; SYSCR2<SYSCK> = 1
; (Switches the main system clock to the basic clock for the low-frequen-
; Waits for 2 machine cycles
; SYSCR2<XEN> = 0
; P0FC2 = 1
; WUCCR<WUCDIV> = 00 (No division)
; Sets the warm-up time
; Enables INTWUC interrupts
; SYSCR2<XTEN> = 1
; SYSCR2<SYSCK> = 1
; Waits for 2 machine cycles
; SYSCR2<XEN> = 0 (Turns off the high-frequency clock oscillation cir-
; INTWUC vector table
cy clock for the SLOW2 mode)
(Turns off the high-frequency clock oscillation circuit)
(Uses P02/03 as oscillators)
WUCCR<WUCSEL> = 1 (Selects fs as the source clock)
(Determines the time depending on the oscillator characteristics)
100 ms/1.95 ms = 51.2 o round up to 0x33
(Starts the low-frequency clock oscillation and starts the warm-up
counter)
(Switches the main system clock to the low-frequency clock)
cuit)
RESET
pin, a power-on reset and a reset by the
TMP89FM42