tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 89

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA000
5.3 Functions
Watchdog timer source clock
Watchdog timer status
5.3.1 Setting of enabling/disabling the watchdog timer operation
(0x0FD7)
WDST
counter and detecting releasing of the 8-bit up counter outside the clear time.
counter at random times and comparing the value to the last read value.
Interrupt request signal
8-bit up counter value
Note 1: WDST<WINTST2> and WDST<WINTST1> are cleared to "0" by reading WDST.
Note 2: Values after reset are read from bits 7 to 3 of WDST.
The watchdog timer can detect the CPU malfunctions and deadlock by detecting the overflow of the 8-bit up
The watchdog timer stoppage and other abnormalities can be detected by reading the count value of the 8-bit up
WDCTR<WDTEN>
WDCTR<WDTEN>
counting the source clock.
means that the watchdog timer is enabled.
Disabling the watchdog timer operation clears the 8-bit up counter to "0".
trol code into WDCDR.
Setting WDCTR<WDTEN> to "1" enables the watchdog timer operation, and the 8-bit up counter starts
WDCTR<WDTEN> is initialized to "1" after the warm-up operation that follows reset is released. This
To disable the watchdog timer operation, clear WDCTR<WDTEN> to "0" and write 0xB1 into WDCDR.
Note:If the overflow of the 8-bit up counter occurs at the same time as 0xB1 (disable code) is written into WDCDR
To re-enable the watchdog timer operation, set WDCTR<WDTEN> to "1". There is no need to write a con-
WINTST2
WINTST1
WDTST
Read/Write
Bit Symbol
After reset
with WDCTR<WDTEN> set at "1", the watchdog timer operation is disabled preferentially and the overflow
detection is not executed.
Figure 5-2 WDCTR<WDTEN> Set Timing and Overflow Time
Watchdog timer interrupt request
signal factor status 2
Watchdog timer interrupt request
signal factor status 1
Watchdog timer operating state sta-
tus
1 clock (max.)
R
7
0
-
00H
R
6
1
-
R
5
0
01H
-
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0 :
1 :
0 :
1 :
0 :
1 :
No watchdog timer interrupt request signal has occurred.
A watchdog timer interrupt request signal has occurred due to the over-
flow of the 8-bit up counter.
No watchdog timer interrupt request signal has occurred.
A watchdog timer interrupt request signal has occurred due to releasing of
the 8-bit up counter outside the clear time.
Operation disabled
Operation enabled
Overflow time
R
4
1
-
Overflow time
R
3
1
-
FFH
WINTST2
R
2
0
WINTST1
1
R
0
00H
TMP89FM42
WDTST
R
0
1