tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 40

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.3 System clock controller
2. CPU Core
RA001
2.3.5.4
Note 1: The NORMAL1 and NORMAL2 modes are generically called the NORMAL mode; the SLOW1 and SLOW2 modes are
Note 2: The mode is released by the falling edge of the source clock selected at TBTCR<TBTCK>.
(a) Single-clock mode
(b) Dual-clock mode
called the SLOW mode; the IDLE0, IDLE1 and IDLE2 modes are called the IDLE mode; and the SLEEP0 and SLEEP1
are called the SLEEP mode.
Transition of operation modes
SLEEP1
mode
mode
IDLE0
mode
IDLE2
Figure 2-7 Operation Mode Transition Diagram
SYSCR2<IDLE> = "1"
SYSCR2<IDLE> = "1"
SYSCR2<IDLE> = "1"
Interrupt
Interrupt
Interrupt
SYSCR2<TGHA L T > = "1"
SYSCR2<SYSCK> = "0"
SYSCR2<XTEN> = "0"
SYSCR2<XEN> = "1"
(Note 2)
NORMAL1
NORMAL2
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SLEEP0
SLOW2
SLOW1
mode
mode
mode
mode
mode
IDLE0
mode
(Note 2)
SYSCR2<TGHALT> = "1"
SYSCR2<SYSCK> = "1"
SYSCR2<XEN> = "0"
SYSCR2<XTEN> = "1"
SYSCR1<STOP> = "1"
SYSCR1<STOP> = "1"
SYSCR1<STOP> = "1"
Warm-up completed
STOP mode release
STOP mode release
STOP mode release
Warm-up that
follows reset
release
signal
signal
signal
Reset release
STOP
RESET
TMP89FM42