tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 310

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

20.2 Control
20. 10-bit AD Converter (ADC)
RA001
AD converter control register 2
ADCCR2
(0x0035)
Table 20-1 ACK Settings and Conversion Times Relative to Frequencies
Note 1: Spaces indicated by "-" in the above table mean that it is prohibited to establish conversion times in these spaces.
Note 2: Above conversion times do not include the time shown below.
Note 3: The conversion time must be longer than the following time by analog reference voltage (VAREF).
Note 1: Make sure that you make the ACK setting when AD conversion is in a halt condition (ADCCR2<ADBF>="0").
Note 2: Make sure that you write "0" to bit 3 of ADCCR2.
Note 3: If STOP, IDLE0 or SLOW mode is started, EOCF and ADBF are initialized to "0".
Note 4: If the AD converted value register (ADCDRH) is read, EOCF is cleared to "0". It is also cleared to "0" if AD conversion is
Note 5: If an instruction to read ADCCR2 is executed, 0 is read from bits 3 through 5.
ACK setting
000
001
010
011
100
101
11*
started (ADCCR1<ADRS>="1") without reading ADCDRH after completing AD conversion in single mode.
fcgck: High Frequency oscillation clock [Hz]
If ACK = 00*, the longest conversion time is 10/fcgck (s). If ACK = 01*, it is 32/fcgck (s). If ACK = 10*, it is 128/fcgck(s).
Read/Write
- Time from when ADCCR1<ADRS> is set to 1 to when AD conversion is started
- Time from when AD conversion is finished to when a converted value is stored in ADCDRL and ADCDRH.
- VAREF = 4.5 to 5.5 V
- VAREF = 2.7 to 5.5 V
- VAREF = 2.2 to 5.5 V
Bit Symbol
After reset
EOCF
ADBF
ACK
Conversion
1248/fcgck
156/fcgck
312/fcgck
624/fcgck
39/fcgck
78/fcgck
time
AD conversion end flag
AD conversion BUSY flag
AD conversion time select (exam-
ples of AD conversion time are
shown in the table below)
EOCF
124.8 Ps
R
7
0
10MHz
15.6 Ps
31.2 Ps
62.4 Ps
-
-
15.6 Ps or longer
31.2 Ps or longer
124.8 Ps or longer
156.0 Ps
19.5 Ps
39.0 Ps
78.0 Ps
ADBF
8MHz
R
6
0
-
-
156.0 Ps
19.5 Ps
39.0 Ps
78.0 Ps
4MHz
-
-
R
5
0
-
Page 296
000:
001:
010:
100:
101:
011:
110:
111:
0:
1:
0:
1:
156.0 Ps
19.5 Ps
39.0 Ps
78.0 Ps
2MHz
Before conversion or during conversion
Conversion end
AD conversion being halted
AD conversion being executed
39/fcgck
78/fcgck
156/fcgck
312/fcgck
624/fcgck
1248/fcgck
Reserved
Reserved
-
-
Reserved
Frequency (fcgck)
R
4
0
-
124.8 Ps
15.6 Ps
31.2 Ps
62.4 Ps
5MHz
-
-
"0"
W
3
0
124.8 Ps
2.5MHz
15.6 Ps
31.2 Ps
62.4 Ps
-
-
156.0 Ps
39.0 Ps
78.0 Ps
1MHz
2
0
-
-
-
156.0 Ps
0.5MHz
78.0 Ps
ACK
R/W
-
-
-
-
1
0
156.0 Ps
TMP89FM42
MHz
0.25
-
-
-
-
-
0
0