tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 92
tmp89fm42
Manufacturer Part Number
tmp89fm42
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP89FM42.pdf
(408 pages)
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5.3 Functions
5. Watchdog Timer (WDT)
RA000
5.3.6 Reading the 8-bit up counter
5.3.7 Reading the watchdog timer status
Watchdog timer interrupt request signal
When WDCTR<WDTW> is 10
Writing of 4EH (clear code)
Reading of WDST
WDST<WINTST1>
WDST<WINTST2>
value to the last read value.
the watchdog timer operation is disabled.
of the 8-bit up counter.
for releasing the 8-bit up counter outside the clear time.
WDST<WINTST2> and WDST<WINTST1> in the watchdog timer interrupt service routine.
same time as the condition for turning WDST<WINTST2> or WDST<WINTST1> to "1" is satisfied,
WDST<WINTST2> or WDST<WINTST1> is set to "1", rather than being cleared.
The counter value of the 8-bit up counter can be read by reading WDCNT.
The stoppage of the 8-bit up counter can be detected by reading WDCNT at random times and comparing the
The watchdog timer status can be read at WDST.
WDST<WDTST> is set to "1" when the watchdog timer operation is enabled, and it is cleared to "0" when
WDST<WINTST2> is set to "1" when a watchdog timer interrupt request signal occurs due to the overflow
WDST<WINTST1> is set to "1" when a watchdog timer interrupt request signal occurs due to the operation
You can know which factor has caused a watchdog timer interrupt request signal by reading
WDST<WINTST2> and WDST<WINTST1> are cleared to "0" when WDST is read. If WDST is read at the
8-bit up counter value
Figure 5-4 Changes in the Watchdog Timer Status
FFH
00H 01H
Interrupt request signal generated by clearing
the 8-bit up counter outside the clear time
Outside the clear time
3FH 40H
Page 78
7FH 80H
BFH C0H
Clear time
FFH 00H
Interrupt request signal generated by the
overflow of the 8-bit up counter
01H
TMP89FM42
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