tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 70

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.5 Interrupt Sequence
3. Interrupt Control Circuit
RA003
Example :SP setting
3.5 Interrupt Sequence
3.5.1 Initial Setting
3.5.2 Interrupt acceptance processing
“0”
the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI]
(for maskable interrupts) or [RETN] (for non-maskable interrupts).
An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to
by resetting or an instruction. Interrupt acceptance sequence requires 8-machine cycles after the completion of
pointing at the start address of a stack. The SP is post-decremented when a subroutine call or a push instruction
is executed or when an interrupt request is accepted. It is pre-incremented when a return or pop instruction is
executed. Therefore, the stack becomes deeper toward lower stack location addresses. Be sure to reserve a
stack area having an appropriate size based on the SP setting.
interrupt master enable flag (IMF) is “0”.
service program
Using an interrupt requires specifying an SP (stack pointer) for it in advance. The SP is a 16-bit register
The SP is initialized to 00FFH after a reset. If you need to change the SP, do so right after a reset or when the
Interrupt acceptance processing is packaged as follows.
Note:When the contents of PSW are saved on the stack, the contents of register bank and IMF are also saved.
Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt
1. The interrupt master enable flag (IMF) is cleared to “0” in order to disable the acceptance of any fol-
2. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.
3. The contents of the program counter (PC) and the program status word, including the interrupt master
4. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the
5. The instruction stored at the entry address of the interrupt service program is executed.
lowing interrupt.
enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Mean-
while, the stack pointer (SP) is decremented by 3.
vector table, is transferred to the program counter.
Figure 3-2 Vector table address and Entry address
LD
LD
ADD
0xFFF4
0xFFF5
Vector table address
0xD2
0x03
SP, 023FH
SP, SP+04H
SP, 0010H
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; SP = 023FH
; SP = SP + 04H
; SP = SP + 0010H
0xD203
0xD204
Vector table address
0x0F
0x06
TMP89FM42