tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 29

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA001
2.3 System clock controller
System control register 1
2.3.1 Configuration
2.3.2 Control
(0x0FDC)
SYSCR1
XTOUT
XOUT
XTIN
XIN
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: Bits 2, 1 and 0 of SYSCR1 are read as "0". Bit 3 is read as "1".
counter and an operation mode control circuit.
(SYSCR2), the warm-up counter control register (WUCCR), the warm-up counter data register (WUCDR) and
the clock gear control register (CGCR).
The system clock controller consists of a clock generator, a clock gear, a timing generator, a warm-up
The system clock controller is controlled by system control register 1 (SYSCR1), system control register 2
OUTEN
Read/Write
DV9CK
Bit Symbol
After reset
STOP
RELM
Low-frequency clock
Clock generator
High-frequency
clock oscillation
oscillation circuit
circuit
Activates the STOP mode
Selects the STOP mode release
method
Selects the port output state in the
STOP mode
Selects the input clock to stage 9 of
the divider
STOP
R/W
7
0
Figure 2-3 System Clock Controller
fc
fs
RELM
R/W
6
0
Clock gear control register
(x1/4,x1/2,x1)
Clock gear
WUCCR
OUTEN
FCGCKSEL
R/W
Oscillation/stop control
Warm-up counter
5
0
Page 15
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
Operate the CPU and the peripheral circuits
Stop the CPU and the peripheral circuits (activate the STOP mode)
Edge-sensitive release mode (Release the STOP mode at the rising edge
of the STOP mode release signal)
Level-sensitive release mode (Release the STOP mode at the "H" level of
the STOP mode release signal)
High impedance
Output hold
fcgck/2
fs/4
WUCDR
DV9CK
R/W
STOP
9
4
0
fcgck
1/4
XEN/XTEN
R
3
1
-
INTWUC interrupt
TBTCR
System clock
generator
R
Timing
2
0
-
DV9CK
1
R
0
-
SYSCR1
System control register
Operation mode
TMP89FM42
control circuit
SYSCR2
R
0
0
-