tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 293

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA001
Example :Generate the start condition
SCL0 pin
SDA0 pin
SBI0CR1<PIN>
SBI0CR2<TRX>
Interrupt request
signal
18.5.3 1-word data transfer
18.5.3.1 When SBI0SR2<MST> is "1" (Master mode)
whether the mode is a master or slave.
Check SBI0SR2<MST> by the interrupt process after a 1-word data transfer is completed, and determine
CHK_BB:
Figure 18-17 Generating the Start Condition and the Slave Address
(1)
Check SBI0SR2<TRX> and determine whether the mode is a transmitter or receiver.
ment the process to generate a stop condition (described later) and terminate data transfer.
ted subsequently is other than 8 bits, set SBI0CR1<BC> again, set SBI0CR1<ACK> to "1", and
write the transmitted data to SBI0DBR.
ring the subsequent 1-word data from the SCL0 pin, and then the 1-word data is transmitted from the
SDA0 pin.
SCL0 pin is set to the low level. If the data to be transferred is more than one word in length, repeat
the procedure from the SBI0SR2<LRB> checking above.
Start condition
When SBI0SR2<TRX> is "1" (Transmitter mode)
Check SBI0SR2<LRB>. When SBI0SR2<LRB> is "1", a receiver does not request data. Imple-
When SBI0SR2<LRB> is "0", the receiver requests subsequent data. When the data to be transmit-
After writing the data, SBI0CR2<PIN> becomes "1", a serial clock pulse is generated for transfer-
After the data is transmitted, an interrupt request occurs. SBI0CR2<PIN> become "0" and the
TEST
JR
LD
LD
1
2
(SBI0SR2).BB
F, CHK_BB
(SBI0DBR), 0xcb
(SBI0CR2), 0xf8
3
Slave address + Direction bit
4
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5
; Confirms that the bus is free
; The transmission slave address 0x65 and the direction bit "1"
; Write "1" to SBI0CR2<MST>, <TRX>, <BB> and <PIN> to "1"
6
7
SBI0CR2 <TRX> is cleared to "0" when
the direction bit is "1"and an
acknowledge signal is returned.
8
9
Acknowledgem
ent signal from
a slave
TMP89FM42