tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 285

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA001
18.4.4.2 Clock synchronization
when the stop condition is generated is t
SCL pin is t
period must be 5/fcgck[s] or longer for the externally input clock, regardless of the SBI0CR1<SCK> set-
ting.
which pulls down a clock pulse to low will, in the first place, invalidate the clock pulse of another master
device which generates a high-level clock pulse. Therefore, the master outputting the high level must
detect this to correspond to it.
transfer even if there are two or more masters on the same bus.
bus.
Note: There are cases where the HIGH period differs from t
In the master mode, the hold time when the start condition is generated is t
When SBI0CR2<PIN> is set to "1" in the slave mode, the time that elapses before the release of the
In both the master and slave modes, the high level period must be 3/fcgck[s] or longer and the low level
In the I
The serial bus interface circuit has a clock synchronization function. This function ensures normal
The example explains clock synchronization procedures when two masters simultaneously exist on a
edge of the SCL pin becomes blunt due to the load capacity of the bus.
SCL input
SCL output
2
C bus, due to the structure of the pin, in order to drive a bus with a wired AND, a master device
LOW
[s].
Figure 18-6 SCL Output
t
HIGH
Figure 18-7 SCL Input
t
HIGH
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t
HIGH
LOW
t
fscl = 1/(t HIGH +
t LOW
HIGH
[s].
= m / fcgck
= n / fcgck
t
t LOW
HIGH
t
LOW
HIGH
>=
>=
t LOW
1/fscl
selected at SBI0CR1<SCK> when the rising
)
HIGH
[s] and the setup time
TMP89FM42