tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 49

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA001
Quarter of the low-frequency clock
Figure 2-12 Switching of the Main System Clock (fm) (Switching from fcgck to fs/4)
2.3.6.4
SYSCR2<SYSCK>
Main system clock
Gear clock (fcgck)
(1)
(2)
SLOW mode
(1)
The SLOW mode is controlled by system control register 2 (SYSCR2).
TBTCR<TBTCK> is detected. After the IDLE0 or SLEEP0 mode is released, the operation is
restarted by the instruction that follows the IDLE0 or SLEEP0 mode start instruction.
TBTCR<TBTCK> is detected. After the release, the INTTBT interrupt processing is started.
main system clock (fm) is switched to fs/4.
off the high-frequency clock oscillator.
warm-up counter before implementing the procedure described above.
(fs/4)
Normal release mode (IMF, EF5, TBTCR<TBTEN> = "0")
The IDLE0 or SLEEP0 mode is released when the falling edge of the source clock selected at
When TBTCR<TBTEN> is "1", the time base timer interrupt latch is set.
Interrupt release mode (IMF, EF5, TBTCR<TBTEN> = "1")
The IDLE0 or SLEEP0 mode is released when the falling edge of the source clock selected at
Note 1: The IDLE0 or SLEEP0 mode is released to the NORMAL1 or SLOW1 mode by the asynchro-
Note 2: When a watchdog timer interrupt is generated immediately before the IDLE0 or SLEEP0 mode
Switching from the NORMAL2 mode to the SLOW1 mode
Set SYSCR2<SYSCK> to "1".
When a maximum of 2/fcgck + 10/fs [s] has elapsed since SYSCR2<SYSCK> is set to "1", the
After switching, wait for 2 machine cycles or longer, and then clear SYSCR2<XEN> to "0" to turn
If the oscillation of the low-frequency clock (fs) is unstable, confirm the stable oscillation at the
Note 1: Be sure to follow this procedure to switch the operation from the NORMAL2 mode to the
Note 2: It is also possible to allow the basic clock for the high-frequency clock to oscillate continuously to
Note 3: After switching SYSCR2<SYSCK>, be sure to wait for 2 machine cycles or longer before clear-
Note 4: When the main system clock (fm) is switched, the gear clock (fcgck) is synchronized with the
nous internal clock selected at TBTCR<TBTCK>. Therefore, the period from the start to the
release of the mode may be shorter than the time specified at TBTCR<TBTCK>.
is started, the watchdog timer interrupt will be processed but the IDLE0 or SLEEP0 mode will
not be started.
SLOW1 mode.
return to NORMAL2 mode. However, be sure to turn off the oscillation of the basic clock for the
high-frequency clock when the STOP mode is started from the SLOW mode.
ing SYSCR2<XEN> to "0". Clearing it within 2 machine cycles causes a system clock reset.
clock that is a quarter of the basic clock (fs) for the low-frequency clock. For the synchronization,
fm is stopped for a period of 10/fs or shorter.
When the rising edge of fcgck is
detected twice after SYSCR2<SYSCK>
is changed from 0 to 1, f is stopped
for synchronization.
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10/fs (max.)
When the rising edge of fs/4 is detected
twice after fm is stopped, fm is switched to fs.
TMP89FM42