tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 331
tmp89fm42
Manufacturer Part Number
tmp89fm42
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP89FM42.pdf
(408 pages)
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RA003
sAddConv:
sAddConvEnd:
; Interrupt subrou-
tine
sINTWDT:
sINTSWI:
Note 1: In using a write instruction in the xxx bus write cycle, make sure that you use a write instruction of
Note 2: If a read of the flash memory (toggle operation) is to be performed after a write instruction is gener-
more than three machine cycles or arrange write instructions in such a way that they are generated at
intervals of three or more machine cycles. If a 16-bit transfer instruction is used or if write instructions
are executed at intervals of two machine cycles, the flash memory command sequence will not be
transmitted properly, and a malfunction may occur.
ated in the xth bus write cycle, instructions must be arranged in such a way that they are generated at
intervals of three or more machine cycles; machine cycles are counted from when the last xth bus
write cycle is generated to when each instruction is generated. Three NOP instructions are normally
used. If the interval between instructions is short, the toggle bit does not operation correctly.
LD
SWAP
AND
SWAP
AND
OR
XOR
SHRC
OR
LD
LD
LD
TEST
J
OR
LD
RET
:
RETN
:
RETN
WA,IX
C
C,0x10
W
W,0x08
C,W
C,0x08
C
C,0xA0
(FLSCR1),C
(FLSCR2),0xD5
WA,IX
C.3
Z,sAddConvEnd
W,0x80
IX,WA
:
:
Page 317
; Enable the execution of command sequence. Make the
FAREA setting.
; Reflect the FLSCR1 setting
; Error processing
; Error processing
TMP89FM42
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