tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 279

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA001
Serial bus interface control register 2
SBI0CR2
(0x0023)
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock oscillation circuit clock
Note 2: Don't change the contents of the registers when the start condition is generated, the stop condition is generated or the
Note 3: After a software reset is generated, all the bits of SBI0CR2 register except SBI0CR2<SBIM> and the SBI0CR1, I2C0AR
Note 4: When the operation is switched to STOP, IDLE0 or SLOW mode, the SBI0CR2 register, except SBI0CR2<SBIM>, and the
Note 5: When fcgck is 4MHz, SCK should be not set to 0y000, 0y001 or 0y010 because it is not possible to satisfy the bus speci-
NOACK
ACK
SCK
BC
data transfer is in progress. Write data to the registers before the start condition is generated or during the period from
when an interrupt request is generated for stopping the data transfer until it is released.
and SBI0SR2 registers are initialized.
SBI0CR1, I2C0AR and SBI0DBR registers are initialized.
fication of fast mode.
Read/Write
Bit Symbol
After reset
Number of data bits
Generation and counting
of the clocks for an
acknowledge signal
Enables/disables the
slave address match
detection and the GEN-
ERAL CALL detection
HIGH and LOW periods
of the serial clock in the
master mode
Time before the release
of the SCL pin in the
slave mode
MST
W
7
0
NOACK
TRX
W
6
0
000:
001:
010:
100:
101:
ACK
SCK
000:
001:
010:
100:
101:
011:
110:
111:
011:
110:
111:
BC
0:
1:
0:
1:
Not generating the clocks for an
acknowledge signal. Generate an
interrupt request when the data
transfer is finished
(non-acknowledgement mode)
Generate the clocks for an
acknowledge signal and an inter-
rupt request when the data trans-
fer is finished
(acknowledgement mode)
clocks for data
t
HIGH
Number of
transfer
BB
W
5
0
(m/fcgck)
Page 265
135
263
15
23
39
71
11
m
8
1
2
3
4
5
6
7
9
Master mode
Master mode
Don’t Care
Don’t Care
ACK=0
Number of data
PIN
t
W
4
1
LOW
(n/fcgck)
bits
138
266
12
14
18
26
42
74
8
1
2
3
4
5
6
7
n
SBIM
W
3
0
Generate an interrupt request when the
data transfer is finished
(non-acknowledgement mode)
Count the clocks for an acknowledge signal
and generate an interrupt request when the
data transfer is finished
(acknowledgement mode)
Enable the slave address match detection
and the GENERAL CALL detection
Disable the slave address match detection
and the GENERAL CALL detection
Number of clocks
for data transfer
fscl@fcgck=
381KHz
320KHz
242KHz
163KHz
99KHz
55KHz
29KHz
15KHz
8MHz
9
2
3
4
5
6
7
8
R
2
0
-
Slave mode
Slave mode
ACK=1
Number of data bits
Reserved (Note5)
Reserved (Note5)
Reserved (Note5)
fscl@fcgck=
1
82KHz
49KHz
28KHz
15KHz
4MHz
8KHz
SWRST
8
1
2
3
4
5
6
7
W
TMP89FM42
0
0