tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 51

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA001
Quarter of the low-frequency clock
Figure 2-13 Switching the Main System Clock (fm) (Switching from fs/4 to fcgck)
PINTWUC:
VINTWUC:
SYSCR2<SYSCK>
Gear clock (fcgck)
Main system clock
Example : Switching from the SLOW1 mode to the NORMAL1 mode after the stability of the high-frequency clock oscilla-
(fs/4)
; #### Initialize routine ####
SET
LD
LD
SET
SET
; #### Interrupt service routine of warm-up counter interrupts ####
CLR
NOP
NOP
CLR
RETI
DW
tion circuit is confirmed at the warm-up counter (fc = 10 MHz, warm-up time = 4.0 ms)
¦
¦
¦
¦
(P0FC).2
(WUCCR), 0x09
(WUCDR), 0x9D
(EIRL). 4
(SYSCR2) .6
(SYSCR2). 4
(SYSCR2). 5
PINTWUC
When the rising edge of fs/4 is
detected twice after SYSCR2<SYSCK>
is changed from 1 to 0, f is stopped
for synchronization.
Page 37
; P0FC2 = 1
; WUCCR<WUCDIV> = 10 (Divided by 2)
; Sets the warm-up time
; Enables INTWUC interrupts
; SYSCR2<XEN> = 1
; SYSCR2<SYSCK> = 0
; Waits for 2 machine cycles
; SYSCR2<XTEN> = 0
; INTWUC vector table
(Uses P02/03 as oscillators)
WUCCR<WUCSEL> = 0 (Selects fc as the source clock)
(Determine the time depending on the frequency and the oscillator
characteristics)
4ms / 25.6us = 156.25 o round up to 0x9D
(Starts the oscillation of the high-frequency clock oscillation circuit)
(Switches the main system clock to the gear clock)
(Turns off the low-frequency clock oscillation circuit)
2.5/fcgck(max.)
When the rising edge of fcgck is detected
twice after fm is stopped, fm is switched to fcgck.
TMP89FM42