tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 225

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA001
UART0 control register 2
UART0 baud rate register
UART0 status register
UART0CR2
UART0DR
UART0SR
(0x001C)
(0x001D)
(0x001B)
Note 1: When a read instruction is executed on UART0CR2, bits 7 and 6 are read as "0".
Note 2: RTSEL can be set to two kinds of RT clocks for the even- and odd-numbered bits of the transfer frame. For details, refer to
Note 3: For details of the RXDNC noise rejection time, refer to "16.10 Received Data Noise Rejection".
Note 4: When the STOP, IDLE0 or SLEEP0 mode is activated, the UART stops automatically but each bit value of UART0CR2
Note 5: When STOPBR is set to 2 bits, the first bit of the stop bits (during data receiving) is not checked for a framing error.
Note 6: To prevent RTSEL, RXDNC and STOPBR from being changed accidentally during the UART communication, the register
Note 1: Set UART0CR1<RXE> and UART0CR1<TXE> to "0" before changing UART0DR. For the set values, refer to "16.8 Trans-
Note 2: When UART0CR1<BRG> is set to the TCA0 output, the value set to UART0DR has no meaning.
Note 3: When the STOP, IDLE0 or SLEEP0 mode is activated, the UART stops automatically but each bit value of UART0DR
"16.8.1 Transfer baud rate calculation method".
remains unchanged.
cannot be rewritten during the UART operation. For details, refer to "16.4 Protection to Prevent UART0CR1 and
UART0CR2 Registers from Being Changed".
fer Baud Rate".
remains unchanged.
STOPBR
RXDNC
Read/Write
Read/Write
RTSEL
Bit Symbol
Bit Symbol
Read/Write
After reset
After reset
Bit Symbol
After reset
Selects the number of RT clocks
Selects the RXD input noise rejec-
tion time
(Time of pulses to be removed as
noise)
Receive stop bit length
UART0DR7
PERR
R/W
R
7
0
7
0
R
7
0
-
UART0DR6
FERR
R/W
R
6
0
6
0
6
R
0
-
UART0DR5
OERR
R/W
R
5
0
5
0
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5
0
000:
001:
010:
011:
100:
101:
11*:
00:
01:
10:
11:
0:
1:
No noise rejection
1 x (UART0DR+1)/(Transfer base clock frequency) [s]
2 x (UART0DR+1)/(Transfer base clock frequency) [s]
4 x (UART0DR+1)/(Transfer base clock frequency) [s]
1 bit
2 bits
UART0DR4
RTSEL
R/W
R/W
R
4
0
4
0
-
4
0
Odd-numbered bits
of transfer frame
16 clocks
16 clocks
15 clocks
15 clocks
17 clocks
UART0DR3
RBSY
R/W
R
3
0
3
0
3
0
UART0DR2
Reserved
Reserved
RBFL
R/W
R
2
0
2
0
2
0
RXDNC
R/W
Even-numbered bits
UART0DR1
of transfer frame
TBSY
R/W
16 clocks
17 clocks
15 clocks
16 clocks
17 clocks
1
0
1
R
0
1
0
TMP89FM42
UART0DR0
STOPBR
TBFL
R/W
R/W
R
0
0
0
0
0
0