tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 61

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA003
3. Interrupt Control Circuit
of the internal interrupt sources are non-maskable while the rest are maskable.
tor addresses. When a request for an interrupt is generated, its interrupt latch is set to "1", which requests the CPU to
accept the interrupt. Acceptance of interrupts is enabled or disabled by software using the interrupt master enable
flag (IMF) and individual enable flag (EF) for each interrupt source. If multiple maskable interrupts are generated
simultaneously, the interrupts are accepted in order of descending priority. The priorities are determined by the inter-
rupt priority change control register (ILPRS1-ILPRS6) as Levels and determined by the hardware as the basic prior-
ities.
The TMP89FM42 has a total of 25 interrupt sources excluding reset. Interrupts can be nested with priorities. Three
Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and have independent vec-
However, there are no prioritized interrupt sources among non-maskable interrupts.
Note 1: To use the watchdog timer interrupt (INTWDT), clear WDCTR<WDTOUT> to "0" (It is set for the "Reset request" after
Note 2: 0xFFFA and 0xFFFB function not as interrupt vectors but as option codes in the serial PROM mode. For details, see
Note 3: Vector address areas can be changed by the SYSCR3<RVCTR> setting. To assign vector address areas to RAM, set
Internal/
External
External
External
External
External
External
External
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
-
-
reset is released). For details, see "Watchdog Timer".
"Serial PROM Mode".
SYSCR3<RVCTR> to "1" and SYSCR3<RAREA> to "1".
(Reset)
INTSWI
INTUNDEF
INTWDT
INTWUC
INTTBT
INTRXD0 / INTSIO0
INTTXD0
INT5
INTVLTD
INTADC
INTRTC
INTTC00
INTTC01
INTTCA0
INTSBI0/INTSIO0
INT0
INT1
INT2
INT3
INT4
INTTCA1
INTRXD1
INTTXD1
INTTC02
INTTC03
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-
Interrupt sources
Non-maskable
Non-maskable
Non-maskable
Non-maskable
IMF AND EIRL<EF4> = 1
IMF AND EIRL<EF5> = 1
IMF AND EIRL<EF6> = 1
IMF AND EIRL<EF7> = 1
IMF AND EIRH<EF8> = 1
IMF AND EIRH<EF9> = 1
IMF AND EIRH<EF10> = 1
IMF AND EIRH<EF11> = 1
IMF AND EIRH<EF12> = 1
IMF AND EIRH<EF13> = 1
IMF AND EIRH<EF14> = 1
IMF AND EIRH<EF15> = 1
IMF AND EIRE<EF16> = 1
IMF AND EIRE<EF17> = 1
IMF AND EIRE<EF18> = 1
IMF AND EIRE<EF19> = 1
IMF AND EIRE<EF20> = 1
IMF AND EIRE<EF21> = 1
IMF AND EIRE<EF22> = 1
IMF AND EIRE<EF23> = 1
IMF AND EIRD<EF24> = 1
IMF AND EIRD<EF25> = 1
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Page 47
Enable condition
ILH<IL10>
ILH<IL11>
ILH<IL12>
ILH<IL13>
ILH<IL14>
ILH<IL15>
ILE<IL16>
ILE<IL17>
ILE<IL18>
ILE<IL19>
ILE<IL20>
ILE<IL21>
ILE<IL22>
ILE<IL23>
ILD<IL24>
ILD<IL25>
ILH<IL8>
ILH<IL9>
ILL<IL3>
ILL<IL4>
ILL<IL5>
ILL<IL6>
ILL<IL7>
Interrupt
latch
-
-
-
-
-
RVCTR=0
0xFFEC
0xFFDE
0xFFDC
0xFFDA
0xFFCE
0xFFCC
enabled
0xFFFE
0xFFFC
0xFFFC
0xFFF8
0xFFF6
0xFFF4
0xFFF2
0xFFF0
0xFFEE
0xFFEA
0xFFE8
0xFFE6
0xFFE4
0xFFE2
0xFFE0
0xFFD8
0xFFD6
0xFFD4
0xFFD2
0xFFD0
Vector Address
-
-
(MCU mode)
RVCTR=1
enabled
0x01FC
0x01FC
0x01EE
0x01EC
0x01EA
0x01DE
0x01DC
0x01DA
0x01D8
0x01D6
0x01D4
0x01D2
0x01D0
0x01CE
0x01CC
0x01F8
0x01F6
0x01F4
0x01F2
0x01F0
0x01E8
0x01E6
0x01E4
0x01E2
0x01E0
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-
TMP89FM42
Basic
prior-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
ity
1
2
2
2
5
6
7
8
9
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