s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 103

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
ASSEMBLY SYNTAX
The most significant four bits of the register contents are written to the N,Z,C & V flags respectively.
The expression should symbolise a 32-bit value of which the most significant four bits are written to the N,Z,C and V
flags respectively.
Key:
EXAMPLES
In User mode the instructions behave as follows:
In privileged modes the instructions behave as follows:
{cond}
Rd and Rm
<psr>
<psrf>
<#expression>
MRS - transfer PSR contents to a register
MRS{cond} Rd,<psr>
MSR - transfer register contents to PSR
MSR{cond} <psr>,Rm
MSR - transfer register contents to PSR flag bits only
MSR{cond} <psrf>,Rm
MSR - transfer immediate value to PSR flag bits only
MSR{cond} <psrf>,<#expression>
MSR
MSR
MSR
MRS
MSR
MSR
MSR
MSR
MSR
MSR
MRS
Two-character condition mnemonic. See Table 3-2..
Expressions evaluating to a register number other than R15
CPSR, CPSR_all, SPSR or SPSR_all. (CPSR and CPSR_all are synonyms as are SPSR
and SPSR_all)
CPSR_flg or SPSR_flg
Where this is used, the assembler will attempt to generate a shifted immediate 8-bit field
to match the expression. If this is impossible, it will give an error.
CPSR_all,Rm
CPSR_flg,Rm
CPSR_flg,#0xA0000000
Rd,CPSR
CPSR_all,Rm
CPSR_flg,Rm
CPSR_flg,#0x50000000
SPSR_all,Rm
SPSR_flg,Rm
SPSR_flg,#0xC0000000
Rd,SPSR
; CPSR[31:28] <- Rm[31:28]
; CPSR[31:28] <- Rm[31:28]
; CPSR[31:28] <- 0xA (set N,C; clear Z,V)
; Rd[31:0] <- CPSR[31:0]
; CPSR[31:0] <- Rm[31:0]
; CPSR[31:28] <- Rm[31:28]
; CPSR[31:28] <- 0x5 (set Z,V; clear N,C)
; SPSR_<mode>[31:0]<- Rm[31:0]
; SPSR_<mode>[31:28] <- Rm[31:28]
; SPSR_<mode>[31:28] <- 0xC (set N,Z; clear C,V)
; Rd[31:0] <- SPSR_<mode>[31:0]
ARM INSTRUCTION SET
3-21